Synthesis Tool for Asynchronous Circuits Based on PCFB and PCHB

نویسنده

  • K. Saleh
چکیده

This paper introduces a synthesis tool for template-based synthesis of asynchronous circuits. The tool, named Template Synthesizer (TSYN) and it is a part of a complete asynchronous design flow named Persia. This tool transforms a behavioral description of a circuit to a sized transistor net-list. The input behavioral description must fit into some previously known templates. These templates are general enough to allow implementation of almost all circuit blocks. Finally, an asynchronous ReedSolomon Decoder is synthesized using this tool.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Testable Design of Template based QDI Asynchronous Circuits

Complexity of design and testing are the major obstacle for widespread use of asynchronous circuit in digital circuit design. Template based synthesis of asynchronous circuit is accepted as an effective way to decrease complexity of design of asynchronous circuit. One of the popular pre-designed templates that most synthesis tools use it to synthesis QDI asynchronous circuit is Pre-Charged Full...

متن کامل

Leakage Power Analysis of Asynchronous Pipeline Templates

In this paper we studied accurate static power consumption in five well-known templates used in implementation of asynchronous circuits. The studied templates comprising PCHB, PCFB, STFB, HC and MOUSTRAP have been used to model a 5-stage 2-bit pipeline by HSPICE in 0.18um CMOS technology. In order to analyze the static power consumption, several behavioral studies were conducted and the results...

متن کامل

Low power sub-threshold asynchronous quasi-delay-insensitive 32-bit arithmetic and logic unit based on autonomous signal-validity half-buffer

The authors propose an asynchronous-logic (async) quasi-delay-insensitive (QDI) autonomous signal-validity half-buffer (ASVHB) realisation approach for low power sub-threshold operation (VDD = 0.2 V). There are three key attributes in the proposed ASVHB realisation approach. First, the ASVHB realisation approach embodies integrated autonomous validity signals, which are unique and are used excl...

متن کامل

Delay-Insensitive Ternary Logic

This paper develops a delay-insensitive (DI) digital design paradigm that utilizes ternary logic as an alternative to dual-rail logic for encoding the DATA and NULL states. This new Delay-Insensitive Ternary Logic (DITL) paradigm is compared with other DI paradigms, such as Pre-Charge HalfBuffers (PCHB) and NULL Convention Logic (NCL), showing that DITL significantly outperforms PCHB and NCL in...

متن کامل

A Uniform Approach to the Synthesis of Synchronous and Asynchronous Circuits

In this paper we illustrate the application of a synthesis procedure used for timed asynchronous circuits to the design of synchronous circuits. In addition to providing a uniform synthesis approach, our procedure results in circuits that are significantly smaller and faster than those designed using the synchronous design tool SIS. .

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2004